| Name | wu_sf6_DS-16x10_Grp14041991of20000000_0 |
| Workunit | 274452589 |
| Created | 25 Jul 2026, 19:45:17 UTC |
| Sent | 2 Aug 2026, 12:03:22 UTC |
| Report deadline | 9 Aug 2026, 12:03:22 UTC |
| Received | 2 Aug 2026, 12:19:40 UTC |
| Server state | Over |
| Outcome | Computation error |
| Client state | Compute error |
| Exit status | 193 (0x000000C1) EXIT_SIGNAL |
| Computer ID | 2912523 |
| Run time | |
| CPU time | |
| Validate state | Invalid |
| Credit | 0.00 |
| Device peak FLOPS | 5.68 GFLOPS |
| Application version | Get Decic Fields v4.02 (opencl_amd) x86_64-pc-linux-gnu |
<core_client_version>7.24.1</core_client_version>
<![CDATA[
<message>
process exited with code 193 (0xc1, -63)</message>
<stderr_txt>
@store_reg (%404, %16) (base=0, wrmask=x, legacy_fsat=0)
32 %405 = @load_reg (%14) (base=0, legacy_fabs=0, legacy_fneg=0)
@store_reg (%405, %15) (base=0, wrmask=x, legacy_fsat=0)
// succs: b166
}
block b170: // preds: b167
32 %406 = @load_scratch (%23 (0x0)) (align_mul=256, align_offset=0)
32 %407 = isub %406, %376
@store_scratch (%407, %23 (0x0)) (align_mul=256, align_offset=0, wrmask=x)
// succs: b172
} else {
block b171: // preds: b159
@store_scratch (%30 (0x1), %24 (0x4)) (align_mul=256, align_offset=4, wrmask=x)
@store_scratch (%23 (0x0), %23 (0x0)) (align_mul=256, align_offset=0, wrmask=x)
@store_scratch (%23 (0x0), %27 (0x8)) (align_mul=256, align_offset=8, wrmask=x)
32 %408 = load_const (0x0000000c = 12)
@store_scratch (%23 (0x0), %408 (0xc)) (align_mul=256, align_offset=12, wrmask=x)
@store_scratch (%23 (0x0), %29 (0x10)) (align_mul=256, align_offset=16, wrmask=x)
32 %409 = load_const (0x00000014 = 20)
@store_scratch (%23 (0x0), %409 (0x14)) (align_mul=256, align_offset=20, wrmask=x)
32 %410 = load_const (0x00000018 = 24)
@store_scratch (%23 (0x0), %410 (0x18)) (align_mul=256, align_offset=24, wrmask=x)
32 %411 = load_const (0x0000001c = 28)
@store_scratch (%23 (0x0), %411 (0x1c)) (align_mul=256, align_offset=28, wrmask=x)
@store_scratch (%23 (0x0), %34 (0x20)) (align_mul=256, align_offset=32, wrmask=x)
32 %412 = load_const (0x00000024 = 36)
@store_scratch (%23 (0x0), %412 (0x24)) (align_mul=256, align_offset=36, wrmask=x)
32 %413 = load_const (0x00000028 = 40)
@store_scratch (%23 (0x0), %413 (0x28)) (align_mul=256, align_offset=40, wrmask=x)
32 %414 = load_const (0x0000002c = 44)
@store_scratch (%23 (0x0), %414 (0x2c)) (align_mul=256, align_offset=44, wrmask=x)
32 %415 = load_const (0x00000030 = 48)
@store_scratch (%23 (0x0), %415 (0x30)) (align_mul=256, align_offset=48, wrmask=x)
32 %416 = load_const (0x00000034 = 52)
@store_scratch (%23 (0x0), %416 (0x34)) (align_mul=256, align_offset=52, wrmask=x)
32 %417 = load_const (0x00000038 = 56)
@store_scratch (%23 (0x0), %417 (0x38)) (align_mul=256, align_offset=56, wrmask=x)
32 %418 = load_const (0x0000003c = 60)
@store_scratch (%23 (0x0), %418 (0x3c)) (align_mul=256, align_offset=60, wrmask=x)
32 %419 = load_const (0x00000040 = 64)
@store_scratch (%23 (0x0), %419 (0x40)) (align_mul=256, align_offset=64, wrmask=x)
32 %420 = load_const (0x00000044 = 68)
@store_scratch (%23 (0x0), %420 (0x44)) (align_mul=256, align_offset=68, wrmask=x)
32 %421 = load_const (0x00000048 = 72)
@store_scratch (%23 (0x0), %421 (0x48)) (align_mul=256, align_offset=72, wrmask=x)
32 %422 = load_const (0x0000004c = 76)
@store_scratch (%23 (0x0), %422 (0x4c)) (align_mul=256, align_offset=76, wrmask=x)
32 %423 = load_const (0x00000050 = 80)
@store_scratch (%23 (0x0), %423 (0x50)) (align_mul=256, align_offset=80, wrmask=x)
32 %424 = load_const (0x00000054 = 84)
@store_scratch (%23 (0x0), %424 (0x54)) (align_mul=256, align_offset=84, wrmask=x)
32 %425 = load_const (0x00000058 = 88)
@store_scratch (%23 (0x0), %425 (0x58)) (align_mul=256, align_offset=88, wrmask=x)
32 %426 = load_const (0x0000005c = 92)
@store_scratch (%23 (0x0), %426 (0x5c)) (align_mul=256, align_offset=92, wrmask=x)
32 %427 = load_const (0x00000060 = 96)
@store_scratch (%23 (0x0), %427 (0x60)) (align_mul=256, align_offset=96, wrmask=x)
32 %428 = load_const (0x00000064 = 100)
@store_scratch (%23 (0x0), %428 (0x64)) (align_mul=256, align_offset=100, wrmask=x)
32 %429 = load_const (0x00000068 = 104)
@store_scratch (%23 (0x0), %429 (0x68)) (align_mul=256, align_offset=104, wrmask=x)
32 %430 = load_const (0x0000006c = 108)
@store_scratch (%23 (0x0), %430 (0x6c)) (align_mul=256, align_offset=108, wrmask=x)
32 %431 = load_const (0x00000070 = 112)
@store_scratch (%23 (0x0), %431 (0x70)) (align_mul=256, align_offset=112, wrmask=x)
32 %432 = load_const (0x00000074 = 116)
@store_scratch (%23 (0x0), %432 (0x74)) (align_mul=256, align_offset=116, wrmask=x)
32 %433 = load_const (0x00000078 = 120)
@store_scratch (%23 (0x0), %433 (0x78)) (align_mul=256, align_offset=120, wrmask=x)
32 %434 = load_const (0x0000007c = 124)
@store_scratch (%23 (0x0), %434 (0x7c)) (align_mul=256, align_offset=124, wrmask=x)
32 %435 = load_const (0x00000080 = 128)
@store_scratch (%23 (0x0), %435 (0x80)) (align_mul=256, align_offset=128, wrmask=x)
32 %436 = load_const (0x00000084 = 132)
@store_scratch (%23 (0x0), %436 (0x84)) (align_mul=256, align_offset=132, wrmask=x)
// succs: b172
}
block b172: // preds: b170 b171, succs: b174
} else {
block b173: // preds: b158, succs: b174
}
block b174: // preds: b172 b173
32 %437 = iadd! %371, %369 (0xffffffe1)
32 %438 = b32csel! %372, %437, %371
32 %439 = ineg! %438
32 %440 = i32csel_ge! %341, %438, %439
32 %441 = ine32 %440, %23 (0x0)
// succs: b175 b181
if %441 {
block b175: // preds: b174
32 %442 = bfm %440, %23 (0x0)
32 %443 = isub %359 (0x1f), %440
32 %444 = @load_scratch (%23 (0x0)) (align_mul=256, align_offset=0)
32 %445 = iadd %444, %42 (0xffffffff)
@store_reg (%445, %20) (base=0, wrmask=x, legacy_fsat=0)
32 %446 = ishl %444, %35 (0x2)
32 %447 = load_const (0xfffffffc = -4 = 4294967292)
32 %448 = iadd %24 (0x4), %446
@store_reg (%448, %18) (base=0, wrmask=x, legacy_fsat=0)
@store_reg (%23 (0x0), %19) (base=0, wrmask=x, legacy_fsat=0)
// succs: b176
loop {
block b176: // preds: b175 b179
32 %449 = @load_reg (%20) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %450 = ilt32 %449, %23 (0x0)
// succs: b177 b178
if %450 {
block b177:// preds: b176
break
// succs: b180
} else {
block b178: // preds: b176, succs: b179
}
block b179: // preds: b178
32 %451 = @load_reg (%18) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %452 = @load_scratch (%451) (align_mul=4, align_offset=0)
32 %453 = iand %452, %442
@store_reg (%453, %17) (base=0, wrmask=x, legacy_fsat=0)
32 %454 = ushr %452, %440
32 %455 = @load_reg (%19) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %456 = ishl %455, %443
32 %457 = ior %454, %456
32 %458 = @load_reg (%18) (base=0, legacy_fabs=0, legacy_fneg=0)
@store_scratch (%457, %458) (align_mul=4, align_offset=0, wrmask=x)
32 %459 = @load_reg (%18) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %460 = iadd %459, %447 (0xfffffffc)
@store_reg (%460, %18) (base=0, wrmask=x, legacy_fsat=0)
32 %461 = @load_reg (%20) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %462 = iadd.nsw %461, %42 (0xffffffff)
@store_reg (%462, %20) (base=0, wrmask=x, legacy_fsat=0)
32 %463 = @load_reg (%17) (base=0, legacy_fabs=0, legacy_fneg=0)
@store_reg (%463, %19) (base=0, wrmask=x, legacy_fsat=0)
// succs: b176
}
block b180: // preds: b177, succs: b182
} else {
block b181: // preds: b174, succs: b182
}
block b182: // preds: b180 b181
32 %464 = @load_scratch (%23 (0x0)) (align_mul=256, align_offset=0)
32 %465 = iadd %464, %42 (0xffffffff)
@store_reg (%465, %21) (base=0, wrmask=x, legacy_fsat=0)
// succs: b183
loop {
block b183: // preds: b182 b189
32 %466 = @load_reg (%21) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %467 = ilt32 %466, %23 (0x0)
// succs: b184 b185
if %467 {
block b184:// preds: b183
break
// succs: b190
} else {
block b185: // preds: b183, succs: b186
}
block b186: // preds: b185
32 %468 = @load_reg (%21) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %469 = ishl %468, %35 (0x2)
32 %470 = iadd %27 (0x8), %469
32 %471 = @load_scratch (%470) (align_mul=4, align_offset=0)
32 %472 = ine32 %471, %23 (0x0)
// succs: b187 b188
if %472 {
block b187:// preds: b186
break
// succs: b190
} else {
block b188: // preds: b186, succs: b189
}
block b189: // preds: b188
32 %473 = @load_reg (%21) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %474 = iadd.nsw %473, %42 (0xffffffff)
@store_reg (%474, %21) (base=0, wrmask=x, legacy_fsat=0)
// succs: b183
}
block b190: // preds: b184 b187
32 %475 = @load_reg (%21) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %476 = iadd.nsw %475, %30 (0x1)
@store_scratch (%476, %23 (0x0)) (align_mul=256, align_offset=0, wrmask=x)
32 %477 = ieq32 %476, %23 (0x0)
// succs: b191 b192
if %477 {
block b191:// preds: b190
@store_scratch (%30 (0x1), %24 (0x4)) (align_mul=256, align_offset=4, wrmask=x)
// succs: b193
} else {
block b192: // preds: b190, succs: b193
}
block b193: // preds: b191 b192, succs: b205
} else {
block b194:// preds: b147
@store_reg (%23 (0x0), %22) (base=0, wrmask=x, legacy_fsat=0)
// succs: b195
loop {
block b195: // preds: b194 b198
32 %478 = @load_scratch (%23 (0x0)) (align_mul=256, align_offset=0)
32 %479 = @load_reg (%22) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %480 = ige32 %479, %478
// succs: b196 b197
if %480 {
block b196:// preds: b195
break
// succs: b199
} else {
block b197: // preds: b195, succs: b198
}
block b198: // preds: b197
32 %481 = @load_reg (%22) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %482 = iadd.nsw %481, %30 (0x1)
@store_reg (%482, %22) (base=0, wrmask=x, legacy_fsat=0)
// succs: b195
}
block b199: // preds: b196, succs: b200
loop {
block b200: // preds: b199 b203
32 %483 = @load_scratch (%23 (0x0)) (align_mul=256, align_offset=0)
32 %484 = @load_reg (%22) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %485 = ige32 %484, %483
// succs: b201 b202
if %485 {
block b201:// preds: b200
break
// succs: b204
} else {
block b202: // preds: b200, succs: b203
}
block b203: // preds: b202
32 %486 = @load_reg (%22) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %487 = ishl %486, %35 (0x2)
32 %488 = iadd %27 (0x8), %487
@store_scratch (%23 (0x0), %488) (align_mul=4, align_offset=0, wrmask=x)
32 %489 = @load_reg (%22) (base=0, legacy_fabs=0, legacy_fneg=0)
32 %490 = iadd.nsw %489, %30 (0x1)
@store_reg (%490, %22) (base=0, wrmask=x, legacy_fsat=0)
// succs: b200
}
block b204: // preds: b201, succs: b205
}
block b205: // preds: b193 b204
32 %491 = @load_scratch (%23 (0x0)) (align_mul=256, align_offset=0)
32 %492 = ilt32 %23 (0x0), %491
// succs: b206 b300
if %492 {
block b206: // preds: b205
32 %493 = @load_scratch (%27 (0x8)) (align_mul=256, align_offset=8)
32 %494 = iadd %51, %27 (0x8)
@store_global (%493, %494) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %495 = ilt32 %30 (0x1), %491
// succs: b207 b298
if %495 {
block b207: // preds: b206
32 %496 = load_const (0x0000000c = 12)
32 %497 = @load_scratch (%496 (0xc)) (align_mul=256, align_offset=12)
32 %498 = iadd %496 (0xc), %51
@store_global (%497, %498) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %499 = ilt32 %35 (0x2), %491
// succs: b208 b296
if %499 {
block b208: // preds: b207
32 %500 = @load_scratch (%29 (0x10)) (align_mul=256, align_offset=16)
32 %501 = iadd %29 (0x10), %51
@store_global (%500, %501) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %502 = ilt32 %331 (0x3), %491
// succs: b209 b294
if %502 {
block b209: // preds: b208
32 %503 = load_const (0x00000014 = 20)
32 %504 = @load_scratch (%503 (0x14)) (align_mul=256, align_offset=20)
32 %505 = iadd %503 (0x14), %51
@store_global (%504, %505) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %506 = ilt32 %24 (0x4), %491
// succs: b210 b292
if %506 {
block b210: // preds: b209
32 %507 = load_const (0x00000018 = 24)
32 %508 = @load_scratch (%507 (0x18)) (align_mul=256, align_offset=24)
32 %509 = iadd %507 (0x18), %51
@store_global (%508, %509) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %510 = load_const (0x00000005)
32 %511 = ilt32 %510 (0x5), %491
// succs: b211 b290
if %511 {
block b211: // preds: b210
32 %512 = load_const (0x0000001c = 28)
32 %513 = @load_scratch (%512 (0x1c)) (align_mul=256, align_offset=28)
32 %514 = iadd %512 (0x1c), %51
@store_global (%513, %514) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %515 = load_const (0x00000006)
32 %516 = ilt32 %515 (0x6), %491
// succs: b212 b288
if %516 {
block b212: // preds: b211
32 %517 = @load_scratch (%34 (0x20)) (align_mul=256, align_offset=32)
32 %518 = iadd %34 (0x20), %51
@store_global (%517, %518) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %519 = load_const (0x00000007)
32 %520 = ilt32 %519 (0x7), %491
// succs: b213 b286
if %520 {
block b213: // preds: b212
32 %521 = load_const (0x00000024 = 36)
32 %522 = @load_scratch (%521 (0x24)) (align_mul=256, align_offset=36)
32 %523 = iadd %521 (0x24), %51
@store_global (%522, %523) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %524 = ilt32 %27 (0x8), %491
// succs: b214 b284
if %524 {
block b214: // preds: b213
32 %525 = load_const (0x00000028 = 40)
32 %526 = @load_scratch (%525 (0x28)) (align_mul=256, align_offset=40)
32 %527 = iadd %525 (0x28), %51
@store_global (%526, %527) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %528 = load_const (0x00000009)
32 %529 = ilt32 %528 (0x9), %491
// succs: b215 b282
if %529 {
block b215: // preds: b214
32 %530 = load_const (0x0000002c = 44)
32 %531 = @load_scratch (%530 (0x2c)) (align_mul=256, align_offset=44)
32 %532 = iadd %530 (0x2c), %51
@store_global (%531, %532) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %533 = load_const (0x0000000a = 10)
32 %534 = ilt32 %533 (0xa), %491
// succs: b216 b280
if %534 {
block b216: // preds: b215
32 %535 = load_const (0x00000030 = 48)
32 %536 = @load_scratch (%535 (0x30)) (align_mul=256, align_offset=48)
32 %537 = iadd %535 (0x30), %51
@store_global (%536, %537) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %538 = load_const (0x0000000b = 11)
32 %539 = ilt32 %538 (0xb), %491
// succs: b217 b278
if %539 {
block b217: // preds: b216
32 %540 = load_const (0x00000034 = 52)
32 %541 = @load_scratch (%540 (0x34)) (align_mul=256, align_offset=52)
32 %542 = iadd %540 (0x34), %51
@store_global (%541, %542) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %543 = ilt32 %496 (0xc), %491
// succs: b218 b276
if %543 {
block b218: // preds: b217
32 %544 = load_const (0x00000038 = 56)
32 %545 = @load_scratch (%544 (0x38)) (align_mul=256, align_offset=56)
32 %546 = iadd %544 (0x38), %51
@store_global (%545, %546) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %547 = load_const (0x0000000d = 13)
32 %548 = ilt32 %547 (0xd), %491
// succs: b219 b274
if %548 {
block b219: // preds: b218
32 %549 = load_const (0x0000003c = 60)
32 %550 = @load_scratch (%549 (0x3c)) (align_mul=256, align_offset=60)
32 %551 = iadd %549 (0x3c), %51
@store_global (%550, %551) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %552 = load_const (0x0000000e = 14)
32 %553 = ilt32 %552 (0xe), %491
// succs: b220 b272
if %553 {
block b220: // preds: b219
32 %554 = load_const (0x00000040 = 64)
32 %555 = @load_scratch (%554 (0x40)) (align_mul=256, align_offset=64)
32 %556 = iadd %554 (0x40), %51
@store_global (%555, %556) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %557 = ilt32 %324 (0xf), %491
// succs: b221 b270
if %557 {
block b221: // preds: b220
32 %558 = load_const (0x00000044 = 68)
32 %559 = @load_scratch (%558 (0x44)) (align_mul=256, align_offset=68)
32 %560 = iadd %558 (0x44), %51
@store_global (%559, %560) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %561 = ilt32 %29 (0x10), %491
// succs: b222 b268
if %561 {
block b222: // preds: b221
32 %562 = load_const (0x00000048 = 72)
32 %563 = @load_scratch (%562 (0x48)) (align_mul=256, align_offset=72)
32 %564 = iadd %562 (0x48), %51
@store_global (%563, %564) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %565 = load_const (0x00000011 = 17)
32 %566 = ilt32 %565 (0x11), %491
// succs: b223 b266
if %566 {
block b223: // preds: b222
32 %567 = load_const (0x0000004c = 76)
32 %568 = @load_scratch (%567 (0x4c)) (align_mul=256, align_offset=76)
32 %569 = iadd %567 (0x4c), %51
@store_global (%568, %569) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %570 = load_const (0x00000012 = 18)
32 %571 = ilt32 %570 (0x12), %491
// succs: b224 b264
if %571 {
block b224: // preds: b223
32 %572 = load_const (0x00000050 = 80)
32 %573 = @load_scratch (%572 (0x50)) (align_mul=256, align_offset=80)
32 %574 = iadd %572 (0x50), %51
@store_global (%573, %574) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %575 = load_const (0x00000013 = 19)
32 %576 = ilt32 %575 (0x13), %491
// succs: b225 b262
if %576 {
block b225: // preds: b224
32 %577 = load_const (0x00000054 = 84)
32 %578 = @load_scratch (%577 (0x54)) (align_mul=256, align_offset=84)
32 %579 = iadd %577 (0x54), %51
@store_global (%578, %579) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %580 = ilt32 %503 (0x14), %491
// succs: b226 b260
if %580 {
block b226: // preds: b225
32 %581 = load_const (0x00000058 = 88)
32 %582 = @load_scratch (%581 (0x58)) (align_mul=256, align_offset=88)
32 %583 = iadd %581 (0x58), %51
@store_global (%582, %583) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %584 = load_const (0x00000015 = 21)
32 %585 = ilt32 %584 (0x15), %491
// succs: b227 b258
if %585 {
block b227: // preds: b226
32 %586 = load_const (0x0000005c = 92)
32 %587 = @load_scratch (%586 (0x5c)) (align_mul=256, align_offset=92)
32 %588 = iadd %586 (0x5c), %51
@store_global (%587, %588) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %589 = load_const (0x00000016 = 22)
32 %590 = ilt32 %589 (0x16), %491
// succs: b228 b256
if %590 {
block b228: // preds: b227
32 %591 = load_const (0x00000060 = 96)
32 %592 = @load_scratch (%591 (0x60)) (align_mul=256, align_offset=96)
32 %593 = iadd %591 (0x60), %51
@store_global (%592, %593) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %594 = load_const (0x00000017 = 23)
32 %595 = ilt32 %594 (0x17), %491
// succs: b229 b254
if %595 {
block b229: // preds: b228
32 %596 = load_const (0x00000064 = 100)
32 %597 = @load_scratch (%596 (0x64)) (align_mul=256, align_offset=100)
32 %598 = iadd %596 (0x64), %51
@store_global (%597, %598) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %599 = ilt32 %507 (0x18), %491
// succs: b230 b252
if %599 {
block b230: // preds: b229
32 %600 = load_const (0x00000068 = 104)
32 %601 = @load_scratch (%600 (0x68)) (align_mul=256, align_offset=104)
32 %602 = iadd %600 (0x68), %51
@store_global (%601, %602) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %603 = load_const (0x00000019 = 25)
32 %604 = ilt32 %603 (0x19), %491
// succs: b231 b250
if %604 {
block b231: // preds: b230
32 %605 = load_const (0x0000006c = 108)
32 %606 = @load_scratch (%605 (0x6c)) (align_mul=256, align_offset=108)
32 %607 = iadd %605 (0x6c), %51
@store_global (%606, %607) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %608 = load_const (0x0000001a = 26)
32 %609 = ilt32 %608 (0x1a), %491
// succs: b232 b248
if %609 {
block b232: // preds: b231
32 %610 = load_const (0x00000070 = 112)
32 %611 = @load_scratch (%610 (0x70)) (align_mul=256, align_offset=112)
32 %612 = iadd %610 (0x70), %51
@store_global (%611, %612) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %613 = load_const (0x0000001b = 27)
32 %614 = ilt32 %613 (0x1b), %491
// succs: b233 b246
if %614 {
block b233: // preds: b232
32 %615 = load_const (0x00000074 = 116)
32 %616 = @load_scratch (%615 (0x74)) (align_mul=256, align_offset=116)
32 %617 = iadd %615 (0x74), %51
@store_global (%616, %617) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %618 = ilt32 %512 (0x1c), %491
// succs: b234 b244
if %618 {
block b234: // preds: b233
32 %619 = load_const (0x00000078 = 120)
32 %620 = @load_scratch (%619 (0x78)) (align_mul=256, align_offset=120)
32 %621 = iadd %619 (0x78), %51
@store_global (%620, %621) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %622 = load_const (0x0000001d = 29)
32 %623 = ilt32 %622 (0x1d), %491
// succs: b235 b242
if %623 {
block b235: // preds: b234
32 %624 = load_const (0x0000007c = 124)
32 %625 = @load_scratch (%624 (0x7c)) (align_mul=256, align_offset=124)
32 %626 = iadd %624 (0x7c), %51
@store_global (%625, %626) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %627 = load_const (0x0000001e = 30)
32 %628 = ilt32 %627 (0x1e), %491
// succs: b236 b240
if %628 {
block b236: // preds: b235
32 %629 = load_const (0x00000080 = 128)
32 %630 = @load_scratch (%629 (0x80)) (align_mul=256, align_offset=128)
32 %631 = iadd %629 (0x80), %51
@store_global (%630, %631) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %632 = load_const (0x0000001f = 31)
32 %633 = ilt32 %632 (0x1f), %491
// succs: b237 b238
if %633 {
block b237: // preds: b236
32 %634 = load_const (0x00000084 = 132)
32 %635 = @load_scratch (%634 (0x84)) (align_mul=256, align_offset=132)
32 %636 = iadd %634 (0x84), %51
@store_global (%635, %636) (wrmask=x, access=none, align_mul=4, align_offset=0)
// succs: b239
} else {
block b238: // preds: b236, succs: b239
}
block b239: // preds: b237 b238, succs: b241
} else {
block b240: // preds: b235, succs: b241
}
block b241: // preds: b239 b240, succs: b243
} else {
block b242: // preds: b234, succs: b243
}
block b243: // preds: b241 b242, succs: b245
} else {
block b244: // preds: b233, succs: b245
}
block b245: // preds: b243 b244, succs: b247
} else {
block b246: // preds: b232, succs: b247
}
block b247: // preds: b245 b246, succs: b249
} else {
block b248: // preds: b231, succs: b249
}
block b249: // preds: b247 b248, succs: b251
} else {
block b250: // preds: b230, succs: b251
}
block b251: // preds: b249 b250, succs: b253
} else {
block b252: // preds: b229, succs: b253
}
block b253: // preds: b251 b252, succs: b255
} else {
block b254: // preds: b228, succs: b255
}
block b255: // preds: b253 b254, succs: b257
} else {
block b256: // preds: b227, succs: b257
}
block b257: // preds: b255 b256, succs: b259
} else {
block b258: // preds: b226, succs: b259
}
block b259: // preds: b257 b258, succs: b261
} else {
block b260: // preds: b225, succs: b261
}
block b261: // preds: b259 b260, succs: b263
} else {
block b262: // preds: b224, succs: b263
}
block b263: // preds: b261 b262, succs: b265
} else {
block b264: // preds: b223, succs: b265
}
block b265: // preds: b263 b264, succs: b267
} else {
block b266: // preds: b222, succs: b267
}
block b267: // preds: b265 b266, succs: b269
} else {
block b268: // preds: b221, succs: b269
}
block b269: // preds: b267 b268, succs: b271
} else {
block b270: // preds: b220, succs: b271
}
block b271: // preds: b269 b270, succs: b273
} else {
block b272: // preds: b219, succs: b273
}
block b273: // preds: b271 b272, succs: b275
} else {
block b274: // preds: b218, succs: b275
}
block b275: // preds: b273 b274, succs: b277
} else {
block b276: // preds: b217, succs: b277
}
block b277: // preds: b275 b276, succs: b279
} else {
block b278: // preds: b216, succs: b279
}
block b279: // preds: b277 b278, succs: b281
} else {
block b280: // preds: b215, succs: b281
}
block b281: // preds: b279 b280, succs: b283
} else {
block b282: // preds: b214, succs: b283
}
block b283: // preds: b281 b282, succs: b285
} else {
block b284: // preds: b213, succs: b285
}
block b285: // preds: b283 b284, succs: b287
} else {
block b286: // preds: b212, succs: b287
}
block b287: // preds: b285 b286, succs: b289
} else {
block b288: // preds: b211, succs: b289
}
block b289: // preds: b287 b288, succs: b291
} else {
block b290: // preds: b210, succs: b291
}
block b291: // preds: b289 b290, succs: b293
} else {
block b292: // preds: b209, succs: b293
}
block b293: // preds: b291 b292, succs: b295
} else {
block b294: // preds: b208, succs: b295
}
block b295: // preds: b293 b294, succs: b297
} else {
block b296: // preds: b207, succs: b297
}
block b297: // preds: b295 b296, succs: b299
} else {
block b298: // preds: b206, succs: b299
}
block b299: // preds: b297 b298, succs: b301
} else {
block b300: // preds: b205, succs: b301
}
block b301: // preds: b299 b300
@store_global (%491, %51) (wrmask=x, access=none, align_mul=4, align_offset=0)
32 %637 = @load_scratch (%24 (0x4)) (align_mul=256, align_offset=4)
@store_global (%637, %216) (wrmask=x, access=none, align_mul=4, align_offset=0)
// succs: b303
} else {
block b302: // preds: b1, succs: b303
}
block b303: // preds: b301 b302, succs: b305
} else {
block b304: // preds: b0, succs: b305
}
block b305: // preds: b303 b304, succs: b306
block b306:
}
EE ../src/gallium/drivers/r600/r600_state_common.c:939 r600_shader_select - Failed to build shader variant (type=5) -2
SIGSEGV: segmentation violation
Stack trace (23 frames):
../../projects/numberfields.asu.edu_NumberFields/GetDecics_4.02_x86_64-pc-linux-gnu__opencl_amd[0x424400]
/lib/x86_64-linux-gnu/libc.so.6(+0x45330)[0x773c2e245330]
/lib/x86_64-linux-gnu/libRusticlOpenCL.so.1(+0x521f1e)[0x773c2bd21f1e]
/lib/x86_64-linux-gnu/libRusticlOpenCL.so.1(+0x238f49)[0x773c2ba38f49]
/lib/x86_64-linux-gnu/libRusticlOpenCL.so.1(+0x1d4715)[0x773c2b9d4715]
/lib/x86_64-linux-gnu/libRusticlOpenCL.so.1(+0x1ba2b3)[0x773c2b9ba2b3]
/lib/x86_64-linux-gnu/libRusticlOpenCL.so.1(+0x1ba678)[0x773c2b9ba678]
/lib/x86_64-linux-gnu/libRusticlOpenCL.so.1(+0x1bd2a2)[0x773c2b9bd2a2]
/lib/x86_64-linux-gnu/libRusticlOpenCL.so.1(+0x1bdb45)[0x773c2b9bdb45]
/lib/x86_64-linux-gnu/libRusticlOpenCL.so.1(+0x1f4138)[0x773c2b9f4138]
/lib/x86_64-linux-gnu/libRusticlOpenCL.so.1(+0x1bda32)[0x773c2b9bda32]
/lib/x86_64-linux-gnu/libRusticlOpenCL.so.1(+0x1bdeb0)[0x773c2b9bdeb0]
/lib/x86_64-linux-gnu/libRusticlOpenCL.so.1(+0x1ec12f)[0x773c2b9ec12f]
/lib/x86_64-linux-gnu/libRusticlOpenCL.so.1(+0x1bdd0a)[0x773c2b9bdd0a]
/lib/x86_64-linux-gnu/libRusticlOpenCL.so.1(+0x1db75c)[0x773c2b9db75c]
/lib/x86_64-linux-gnu/libRusticlOpenCL.so.1(+0x1debe6)[0x773c2b9debe6]
/lib/x86_64-linux-gnu/libRusticlOpenCL.so.1(+0x1e3474)[0x773c2b9e3474]
/lib/x86_64-linux-gnu/libRusticlOpenCL.so.1(+0x1e319d)[0x773c2b9e319d]
../../projects/numberfields.asu.edu_NumberFields/GetDecics_4.02_x86_64-pc-linux-gnu__opencl_amd[0x40ce67]
../../projects/numberfields.asu.edu_NumberFields/GetDecics_4.02_x86_64-pc-linux-gnu__opencl_amd[0x40a846]
/lib/x86_64-linux-gnu/libc.so.6(+0x2a1ca)[0x773c2e22a1ca]
/lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0x8b)[0x773c2e22a28b]
../../projects/numberfields.asu.edu_NumberFields/GetDecics_4.02_x86_64-pc-linux-gnu__opencl_amd[0x40b09e]
Exiting...
</stderr_txt>
]]>